Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. The increased density and corresponding decrease in area of the integrated circuit has generally surpassed the ability to bond an integrated circuit chip directly onto a substrate. Accordingly, interposers have been used to redistribute ball contact areas from that of the chip to a larger area of the interposer. Further, interposers have allowed for a three-dimensional (3D) package that includes multiple chips.
Despite the benefits of using an interposer to allow for a reduced size of the chip, using an interposer typically has drawbacks. Interposers generally introduce new sets of problems that go undetected until processing is completed. Thus, packages having faulty interposers may undergo processing that is unnecessary because a defect in earlier processing rendered the interposers unusable. Some of these problems generally include voids in a through substrate via (TSV, also known as a through-silicon via or a through semiconductor via), abnormal routing of a metallization layer after an etch process, a bump cold joint (open or short circuit), and a crack in an interposer ball.